A New Distributed Test Control Architecture with Multihop Wireless Test Connectivity and Communication for GigaHertz System-Chips (Extended Summary)

With the increase in chip size and complexity, the direct or bus interconnects in conventional SoC test control models are rather restricted. In this paper, we propose a new distributed multihop wireless test control network based on the recent development in “radio-on-chip” technology. The proposed architecture consists of three basic components, the test scheduler, the resource configurators, and the RF nodes which support the communication between the test scheduler and clusters of cores. Under the multilevel tree structure, the resources (including not only the circuit blocks to perform testing, but also the on-chip radio-frequency nodes for intra-chip communication) are properly distributed and system optimization is performed in terms of both test application time and test control cost. Topic Category: System-on-Chip (SOC) Test, System Testing, Test Resource Partitioning